Build software better, together

Entropify / Entropic_R32-P5_RISC-V

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

Updated Sep 13, 2026
Python

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

Star

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic

Updated Oct 13, 2025
SystemVerilog

HafizMutahirAhmed / RV32I-5-Stage-Processor

Star

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor

Updated Jul 27, 2025
SystemVerilog

yusronizza / riscv

Star

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

open-source processor-architecture processor risc risc-v processor-design singlecycle-processor pipelined-processor

Updated Jan 7, 2025
Verilog

StackedArchitect / Fault-Tolerant-RISCV

Star

A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor

Updated Jun 26, 2025
Verilog

Pranav-2045 / riscv-5stage-pipelined-matmul

Star

Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.

python matrix-multiplication verilog computer-architecture icarus-verilog hardware-acceleration instruction-set-architecture rv32i processor-design forwarding-unit custom-assembler pipelined-processor risk-v risc-v-processor 32-bit-processor gtk-wave verilog-2001 hazard-handling

Updated Sep 21, 2026
Verilog

EslamAsHhraf / Pipelined-Processor

Star

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor

Updated Oct 16, 2023
Verilog

aGhandhii / pipelined-arm64-processor

Star

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

arm64 systemverilog computer-architecture legv8-arm pipelined-processor

Updated Nov 12, 2023
SystemVerilog

pranav0x2212 / RISCape

Star

RISCape is a 5-stage pipelined RISC-V processor

risc-v rv32i pipelined-processor

Updated Oct 12, 2025
SystemVerilog

helcsnewsxd / armv8-pipelined-hazard-handling

Star

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

python processor-architecture analysis assembly lab university-project forwarding computer-architecture hazard-detection system-verilog armv8 quartus hardware-description-language processor-design famaf pipelined-processor

Updated May 27, 2025
SystemVerilog

raeesiarya / RISCVProcessorFPGA

Star

Four-stage pipelined RV32I/RV32F RISC-V SoC for the PYNQ-Z1, with a custom FPU, UART boot, and on-chip memories. Simulation to bitstream.

cpu fpga processor verilog vivado computer-architecture pynq risc-v rv32i pipelined-processor floating-point-unit

Updated May 25, 2026
Verilog

Krishna-Gorai / 5-stage-pipelined-riscv

Star

Synthesizable 5-stage pipelined RISC-V (RV32I) processor in Verilog. Verified in Vivado 2025.1 through post-implementation functional sim on XC7A200T. Timing met @ 83.33 MHz.

cpu fpga riscv verilog xilinx vivado computer-architecture rv32i pipelined-processor

Updated Jun 18, 2026
Verilog

SaiManojGubbala / RISC-V

Star

A 32 Bit RISC-V Processor Implementation in Verilog

risc-v riscv32 verilog-project pipelined-risc pipelined-processor

Updated Apr 18, 2025
Verilog

oluwaferanmi-arowoshola / riscv-pipelined-processor

Star

SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.

fpga simulation verification xilinx synthesis vivado systemverilog computer-architecture hazard-detection risc-v digital-design rv32i waveform-analysis processor-design cpu-design forwarding-unit rtl-design hardware-design pipelined-processor

Updated May 16, 2026
SystemVerilog

algorhtym / mips-pipelined-processor

Star

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

vhdl mips-architecture risc-processor structural-vhdl pipelined-processor

Updated Apr 11, 2023
VHDL

avnlk / MIPS_Processor

Star

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

mips processor mips-processor pipelined-processor

Updated Mar 29, 2024
Python

cshieldsce / riscv-5i

Star

A 5-stage pipelined RV32I core in SystemVerilog. Full forwarding, load-use stalling, early branch resolution. RISCOF-verified against Spike, synthesized on a Zynq-7000.

cpu fpga verilog xilinx vivado systemverilog computer-architecture risc-v rv32i pynq-z2 riscof pipelined-processor

Updated Sep 14, 2026
SystemVerilog

narenhalubai / 32bit-5-Stage-Pipelined-RISC-Processor

Star

This project is a simple 32-bit pipelined RISC processor built in Verilog. It is based on a MIPS-style architecture and is divided into the five classic pipeline stages: fetch, decode, execute, memory, and write-back. The processor can run basic instructions like addition and memory operations, and the waveform simulation shows how an instruction

processor waveform verilog alu risc 5 32-bit pipelined-processor 5-stage-pipelined-processor

Updated Jun 5, 2026
Verilog

SaheelFaisal / verilog-pipelined-risc-cpu

Star

Structural Verilog implementation of a pipelined RISC CPU datapath and control unit based on Mano & Kime.

verilog computer-architecture icarus-verilog testbench digital-design risc-cpu rtl-design pipelined-processor

Updated Apr 24, 2026
Verilog

Khaledbaniodeh / 32bit-Pipelined-RISC-Processor

Star

A 32-bit five-stage pipelined RISC processor implemented in Verilog HDL with hazard detection and forwarding.

simulation processor assembly verilog computer-architecture hazard-detection risc digital-design forwarding-unit pipelined-processor

Updated Jul 21, 2026
Verilog

Navigation Menu

pipelined-processor

Here are 34 public repositories matching this topic...

Entropify / Entropic_R32-P5_RISC-V

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

HafizMutahirAhmed / RV32I-5-Stage-Processor

yusronizza / riscv

StackedArchitect / Fault-Tolerant-RISCV

Pranav-2045 / riscv-5stage-pipelined-matmul

EslamAsHhraf / Pipelined-Processor

aGhandhii / pipelined-arm64-processor

pranav0x2212 / RISCape

helcsnewsxd / armv8-pipelined-hazard-handling

raeesiarya / RISCVProcessorFPGA

Krishna-Gorai / 5-stage-pipelined-riscv

SaiManojGubbala / RISC-V

oluwaferanmi-arowoshola / riscv-pipelined-processor

algorhtym / mips-pipelined-processor

avnlk / MIPS_Processor

cshieldsce / riscv-5i

narenhalubai / 32bit-5-Stage-Pipelined-RISC-Processor

SaheelFaisal / verilog-pipelined-risc-cpu

Khaledbaniodeh / 32bit-Pipelined-RISC-Processor

Add this topic to your repo