Browser-based Arm micro-architecture simulator with single-cycle and pipelined CPU visualization (educational, simulator)
A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.
Projeto da disciplina de Infraestrutura de Hardware onde o objetivo é criar um pipeline completo e implementação de instruções no processador RISC-V.
A local web editor for CPU pipeline timing tables with stage validation, semantic coloring, forwarding arrows, and Markdown/JSON/PNG export.
Simulador visual de instruções em pipeline de CPU (Fetch, Decode, Execute, Memory, Writeback) e tratamento de hazards.
Simulación didáctica de un procesador RISC de 16 bits con pipeline de 5 etapas
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