Circuits and Systems Lab (CASlab)

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1. UPSET UPSET Public

   UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

   Verilog 9 1

2. LibreEDA LibreEDA Public

   A static timing analysis (STA) engine for open-source EDA flows.

   Verilog 2

3. uth-pexconv uth-pexconv Public

   Parasitic extraction format converters for FasterCap and other field solvers

   Python 1